Product Summary

The CY7C1019CV33-12VC is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion of the CY7C1019CV33-12VC is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. The CY7C1019CV33-12VC has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the CY7C1019CV33-12VC is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) of the CY7C1019CV33-12VC are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019CV33-12VC is available in a standard 32-pin TSOP II and 400-mil-wide SOJ.

Parametrics

CY7C1019CV33-12VC maximum ratings: (1)Storage Temperature: –65℃ to +150℃; (2)Ambient Temperature with Power Applied: –55℃ to +125℃; (3)Supply Voltage on VCC to Relative GND: –0.5V to + 4.6V; (4)DC Voltage Applied to Outputs; (5)in High-Z State: –0.5V to VCC + 0.5V; (6)DC Input Voltage: –0.5V to VCC + 0.5V; (7)Current into Outputs (LOW): 20 mA; (8)Static Discharge Voltage>2001V(per MIL-STD-883, Method 3015); (9)Latch-up Current>200 mA.

Features

CY7C1019CV33-12VC features: (1)Pin and function compatible with CY7C1019BV33; (2)High speed AA = 8, 10, 12, 15 ns; (3)CMOS for optimum speed/power; (4)Data retention at 2.0V; (5)Center power/ground pinout; (6)Automatic power-down when deselected; (7)Easy memory expansion with CE and OE options; (8)Available in 32-pin TSOP II and 400-mil SOJ package.

Diagrams

CY7C1019CV33-12VC Logic Block Diagram

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